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Electronic Data Interchange Format file. An industry standard file format for specifying a design netlist. Generating PartMiner edaXML-Format Files for Use with Other EDA Tools; Generating Board-Level Signal Integrity Analysis Files. Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis; Generating Boundary-Scan Description Language Files. Create Board-Level Boundary-Scan File Window (File Menu) Using Project Revisions. EDIF (Electronic Design Interchange Format) is a vendor-neutral format based on S-Expressions in which to store Electronic netlists and schematics. It was one of the first attempts to establish a neutral data exchange format for the electronic design automation (EDA) industry. EDIF (Electronic Design Interchange Format) is a vendor neutral format in which to store Electronic netlists and schematics. It was one of the first attempts to establish a data exchange format for the electronic design automation (EDA) industry. The goal was to establish a common format from which the proprietary formats of the EDA systems could be derived.

B.4 Electron Beam ExposureUp:B. Layout Data Formats Previous:B.2 Calma GDS II

Subsections

B.3.2 Contents
B.3.3 Interface

This description of EDIF format is taken from Appendix D of Computer Aidsfor VLSI Design by Steven M. Rubin [205].

The Electronic Design Interchange Format (EDIF) is a recent effort atcapturing all aspects of VLSI design in a single representation. This isuseful not only as a communications medium to manufacturing equipment, butalso as an interchange format between CAD systems, since none of thehigh-level information is lost. EDIF is designed to be both easy to read byhumans and easy to parse by machines.EDIF files resemble the LISP programming language because of the use of prefixnotation enclosed in parentheses. For example, the CIF polygon:

P 100 100 150 200 200 100;

look like this in EDIF:

(polygon (point 100 100) (point 150 200) (point 200 100))

All EDIF statements consist of an open parenthesis, a keyword, someparameters, and a close parenthesis. The parameters can be other statements,which is what gives EDIF structure. Actually, an EDIF file contains only onestatement:

(edif parameters)

where parameters are the described circuit.Not only does EDIF resemble LISP, but in its highest level it contains all ofLISP and is an extension of this highly expressive language. However, in theinterest of making parsing simple, there are three levels of EDIF, and lowerlevels are less powerful. Level 1, the intermediate level, allows variables tobe used and cell definitions to be parameterized. EDIF level 0 has noprogrammability and requires constants in all statements. A LISP preprocessorcan translate from EDIF levels 1 or 2 down to level 0, and any given level ofEDIF can be read by a parser of a higher level. Since level 0 is all that isnecessary for most interchange and all manufacturing specification, only thatlevel will be discussed here. Also, some of the EDIF constructs that deal withsimulation, routing, behavior, and other unusual specifications will not becovered in detail.

B.3.1 EDIF Structure

An EDIF file contains a set of libraries, each containing a set of cells. Eachcell can be described with one or more views that show the cell in the form ofa schematic, layout, behavioral specification, document, and more. Each viewhas both an interface and contents so that it is cleanly defined and can belinked to other views with a view map. Libraries may also contain technologyinformation so that defaults can be given for behavior, graphics, and otherattributes. The overall structure of an EDIF file looks like this:

(edif name

(status information) (design where-to-find-them) (external reference-libraries) (library name

(technology defaults) (cell name

(viewmap map) (view type name

(interface external) (contents internal)
)
)
)
)

The status statement is used to track design progress and contains authornames, modification dates, and program versions. Additional status statementsmay appear in each library, cell, and view. The design statement indicateswhere a completed design may be found by pointing to the top cell of ahierarchical description. The external statement names libraries that will beused but are not listed in this EDIF file. The library, cell, and view blockscan be repeated as necessary. There is also a comment statement that can beplaced at the end of most blocks to add readability to the file. Here is anexample of an EDIF file that further illustrates the outer level:

(edif my-design

(status

(edifversion 1 0 0) (ediflevel 0) (written

(timestamp 2004 4 1 11 16 6) (accounting author 'Rainer Minixhofer') (accounting location 'Vienna') (accounting program 'Virtuoso') (comment 'timestamp contains year, month, day, hour,') (comment ' minute, and second')
)
) (design test-chip

(qualify test-library top-cell) (comment 'look for top-cell in test-library')
) (external pad-library pla-library) (library test-library

(technology 0.35-micron-CMOS

..
) (cell top-cell

(viewmap .. ) (view masklayout real-geometry

(interface .. ) (contents .. )
) (view schematic more-abstract

(interface .. ) (contents .. )
)
)
)
)

The written part of a status block may be repeated to show allauthors and update events. Also note that the qualify statement whichnames a cell in a particular library, is generally useful and can appearanywhere that an isolated name may be ambiguous or undefined.

In the following sections, more information is given to describe the contents,interface, viewmap, and technology blocks.

B.3.2 Contents

The contents of a cell may be represented in a number of different waysdepending on the type of data. Each representation is a different view, andmultiple views can be used to define a circuit fully. EDIF accepts sevendifferent view types: netlist for pure topology as is required by simulators,schematic for connected logic symbols, symbolic for more abstract connectiondesigns, mask layout for the geometry of chip and board fabrication,behavior for functional description, document for general textual description, andstranger for any information that cannot fit into the other six view types.The statements allowed in the contents section vary with the view type (seeFig. D.1). The netlist, schematic, and symbolic views are essentially the same,because they describe circuit topology. The allowable statements in theseviews are the declarations Format

define, unused, global, rename, and instance; therouting specifications joined, mustjoin, and criticalsignal; and the timingspecifications required and measured. Schematic and symbolic views also allowthe annotate and wire statements. The mask-layout view allows all of thedeclarations, some of the routing constructs, and the figuregroup statementfor actual graphics. The behavior view allows only a few declarations and thelogicmodel statement. The document view allows only the instanceand section constructs. Finally, the stranger view allows everything but supportsnothing. It should be avoided whenever possible.

Edif Netlist File Format